1. Field of the Invention
The present invention relates to a data processing system and a data processing method for processing serial data, which is transferred over a serial bus in order of issuance of a data output instruction from a single processor or a plurality of processors formed as one chip, and transmitting the resultant data to another chip, and also relates to a computer-readable storage medium and a disk drive.
For example, the present invention is applied to a data processing system adapted to a disk drive (for example, a magnetic disk drive) comprising a disk driver that drives a disk, such as a magnetic disk, and a head driver that drives a head. For control of various motions including a motion for writing information (data) on a disk using a head and a motion for reading information from the disk, the data processing system efficiently processes a large amount of serial data transferred over a serial bus from a single processor or a plurality of processors formed as one chip, and transmits the resultant data to an output control circuit (for example, a read channel (normally abbreviated to RDC)) that is formed as another chip for control of reading or writing.
2. Description of the Related Art
Generally, in storage devices including a disk drive, a main memory is accessible to a processor formed as one chip. In efforts to apparently increase the storage capacity of the main memory, a plurality of memory banks (which hereinafter may be simply called banks) is included in a read channel or the like, which is formed as another chip, for registering data. The memory banks are appropriately switched in use.
For example, assume that serial data is transferred in units of a block from a main memory accessible to a processor formed in one chip, and that one block of serial data comprises twenty bits including eleven address bits, eight data bits, and one reading/writing control bit (R/W bit). Furthermore, the serial data of twenty bits shall be serial data whose four high-order address bits are fixed, whose seven low-order address bits are changeable, and whose eight data bits are changeable. If ten blocks of such serial data are transmitted to another chip, it takes a long time, calculated simply as a product of 20 bits by 10 serial clock cycles, to record the serial data blocks in registers or the like in another chip.
On the other hand, in order to use part of the serial data as bank data, the four high-order bits are separated from the address bits and used to represent an address of a bank (in which serial data of sixteen bits is stored). Seven bits are used as address bits to record data in a register in another chip. In this case, after an address of a bank in which sixteen bits are stored is designated, it takes only the time, calculated simply as a product of 16 bits by 10 serial clock cycles, to record the blocks of data of 16 bits in registers.
In short, assuming that ten blocks of serial data of twenty bits (register designation serial data) transferred from one chip are recorded in registers in another chip, it takes a long time, calculated simply as a time required for registering 200 bits. In contrast, assuming that part (for example, four bits) of serial data is used as serial data (bank designation serial data) with which an address of a bank is designated, it takes only the time, calculated simply as the time required for registering 160 bits. Therefore, when part of the serial data transferred from one chip is treated as bank data, it has the advantage of shortening of the time required for recording serial data blocks in registers in another chip.
Assume that a plurality of processors is formed in one chip, designed as a large-scale integration (LSI) circuit, which treats serial data transferred from one chip as bank data. Under the circumstances, if the plurality of processors accesses data, the data may be stored in registers having consecutive addresses. As the other processor may modify an address of a bank, every time data is transferred in units of a block, an address of a bank must be designated.
Typically, as far as a conventional data processing system that processes serial data transferred from two processors incorporated in a disk drive or the like is concerned, a control unit for controlling various motions including reading and writing motions to be performed in the disk drive is constructed as one chip. The control unit comprises a microcontroller unit (MCU) that is one processor which manages a main memory and which has a memory conversion ability and a memory protection ability, a digital signal processor (DSP) that is the other processor which performs arithmetic operations on a digital signal (data) at a high speed, and a sequencer that transfers data sent from the MCU and DSP over a common serial bus. The MCU converts parallel data into serial data, and transfers the serial data to the sequencer. The DSP performs arithmetic operations on parallel data so as to convert the parallel data into serial data, and transfers the serial data to the sequencer. The sequencer transfers serial data in units of a block over the serial bus in order of issuance of a data output instruction from the MCU and DSP.
Furthermore, the conventional data processing system includes a data output processing unit that processes and transmits serial data transferred from the sequencer over the serial bus. The data output processing unit includes a data output circuit that serves as a buffer circuit mediating between one chip and another chip. The data output circuit receives serial data directly from the control unit, and transmits the serial data to an output control circuit in another chip in a through manner (without a change in the contents of data).
The output control circuit is constituted by a read channel (RDC) for use in controlling reading or writing of data from or into a disk drive. The output control circuit has the ability to record serial data, which is sent from the data output processing unit, in a bank designative register so that the serial data can be used as bank data.
However, assuming that serial data is accessed by the plurality of processors including the MCU and DSP, and recorded in the same bank designative register, if data accessed by the MCU and data accessed by the DSP are mixed, as the other processor (for example, the MCU) may modify an address of a bank, a bank address must be designated at every time of transmitting data in units of a block.
On the other hand, even when one processor is formed in one chip, if other serial data is mixed due to an interrupt caused by an external timer, an address of a bank may be modified. Therefore, the bank address must be designated every time.
In either case, bank designation serial data is transmitted over the serial bus in order to select an address of a bank. Thereafter, register designation serial data with which a register in other chip is designated must be transmitted. In short, in either case, the bank designation serial data and register designation serial data must be transmitted in pairs. Therefore, in the conventional data processing system, as a bank address must be designated every time, it takes a long time to transfer serial data.
On the other hand, when two or more register designation serial data items are transmitted successively, a currently designated address of a bank may be instantaneously modified. Therefore, bank designation serial data is needed every time. When the register designation serial data is transmitted without production of bank designation serial data, if an unexpected interrupt occurs, a completely different register may be designated.
Patent Documents 1 to 3 related to the foregoing conventional disk processing system will be presented below as related art literatures. Patent Document 1 discloses a vector processing system in which an address of an access code recorded in a vector register is detected, and whether the address is accessed continuously is determined. At this time, if the address is recognized to be accessed continuously, a data field of address information on the address is omitted. In the vector processing system, the continuity of addresses in a main memory is emphasized. However, an address of a bank in which current serial data is stored is not compared with an address of a bank in which immediately preceding serial data is stored.
Patent Document 2 discloses a memory control system in which, when successive requests for the same page are recorded, a plurality of accesses is successively achieved quickly in units of a page. Thus, a fast memory system is constructed. However, in the memory control system, an address of a bank in which current serial data is stored is not compared with an address of a bank in which immediately preceding serial data is stored.
Patent Document 3 discloses a memory control circuit that, when memory writing access to the same address is continuously requested, command/address information contained in a succeeding memory request is compared with command/address information which is contained a preceding memory request and with which an accessed bank is designated. If the pieces of command/address information disagree with each other, designation as a busy bank is canceled. Memory access is then performed. If the pieces of command/address information agree with each other, data to be written in the memory is updated with data to be written in response to the succeeding memory request. In reality, memory access is executed only once. However, in the memory control circuit, an address of a bank in which current serial data is stored is not compared with an address of a bank in which immediately preceding serial data is stored.
Consequently, in any of Patent Documents 1 to 3, when serial data transferred from one or two or more processors incorporated in a disk drive is processed, the same problems as those underlying the conventional data processing system take place.
1. Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 5-020350
2. Patent Document 2: Japanese Unexamined Patent Publication (Kokai) No. 9-282223
3. Patent Document 3: Japanese Unexamined Patent Publication (Kokai) No. 11-194969